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Class-D Audio Power Stage ADAU1513
FEATURES
Integrated stereo power stage RDS-ON < 0.3 (per transistor) Efficiency > 90% Short-circuit protection Overtemperature protection
GENERAL DESCRIPTION
The ADAU1513 is a 2-channel bridge-tied load (BTL) Class-D audio power stage. The power stage can drive the speaker loads of 4 at up to 15 W per channel at high efficiency. The 4-channel audio system can be formed when used with an ADAV4201 pulse-width modulator (PWM) processor using two ADAU1513s. The power stage accepts a 3.3 V logic differential PWM as input from an ADAV4201 processor. The power stage comprises thermal and output short-circuit protection with logic-level error flag outputs for interfacing to a system microcontroller along with reset and mute control of the power stage. The power stage operates from a range of power supply voltages from 9 V up to 18 V. The low power digital logic operates from a 3.3 V supply. The power stage can be used with modulators other than the ADAV4201. Contact your local sales department for application assistance.
APPLICATIONS
Flat panel televisions PC audio systems Mini components
FUNCTIONAL BLOCK DIAGRAM
PVDD INL+ A1 INL- A2 PGND PVDD B1 B2 LEVEL SHIFT AND DEAD TIME CONTROL C1 C2 AVDD OUTL- PGND PVDD OUTR+ PGND PVDD VOLTAGE REFERENCE D1 D2 OUTR- PGND OUTL+
INR+ INR-
AGND
DVDD
MODE CONTROL LOGIC
TEMPERATURE/ OVERCURRENT PROTECTION
DGND
STDN MUTE ERR OTW
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06750-001
ADAU1513
ADAU1513 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Performance Summary................................................................ 3 Power Supplies .............................................................................. 3 Digital I/O ..................................................................................... 4 PWM Input Logic Table .............................................................. 4 Digital Timing............................................................................... 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Description .............................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 12 Overview ..................................................................................... 12 Power Stage ................................................................................. 12 Protection Circuits ..................................................................... 12 Thermal Protection.................................................................... 12 Overcurrent Protection ............................................................. 12 Undervoltage Protection ........................................................... 12 Automatic Recovery from Protections .................................... 12 MUTE and STDN ...................................................................... 13 Power-Up/Power-Down Sequence .......................................... 13 Applications Information .............................................................. 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
5/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADAU1513 SPECIFICATIONS
DVDD = 3.3 V, AVDD = 3.3 V, PVDD = 15 V, ambient temperature = 25C, load impedance = 8 , measurement bandwidth = 20 Hz to 20 kHz, unless otherwise noted. Audio performance test data measured with ADAV4201.
PERFORMANCE SUMMARY
Table 1.
Parameter OUTPUT POWER1 Min Typ 11 14 14.5 17.5 19 23 90 280 250 135 150 5 0.1 96 96 65 5 50 Max Unit W W W W W W % m m C C A % dB dB dB V ns Test Conditions/Comments 1 kHz 1% THD + N, 8 10% THD + N, 8 1% THD + N, 6 10% THD + N, 6 1% THD + N, 4 10% THD + N, 4 POUT = 15 W ID = 100 mA ID = 100 mA Die temperature Die temperature peak POUT = 1 W, 1 kHz A-weighted, referred to 1% THD + N output A-weighted, measured with -60 dBFS input @ 0 dBFS input 20 Hz to 20 kHz
EFFICIENCY RDS-ON Per High-Side Transistor Per Low-Side Transistor THERMAL CHARACTERISTICS Thermal Warning Active2 Thermal Shutdown Active OVERCURRENT SHUTDOWN ACTIVE TOTAL HARMONIC DISTORTION PLUS NOISE (THD + N) SIGNAL-TO-NOISE RATIO (SNR) DYNAMIC RANGE CROSSTALK BETWEEN LEFT AND RIGHT CHANNELS UNDERVOLTAGE TRIP THRESHOLD MINIMUM OUTPUT PULSE WIDTH
1 2
Output powers above 15 W at 4 and above 18 W at 6 may need extra heat-sinking for continuous operation. Thermal warning flag is for indication of device TJ reaching close to shutdown temperature.
POWER SUPPLIES
Table 2.
Parameter DIGITAL SUPPLY VOLTAGE (DVDD) ANALOG SUPPLY VOLTAGE (AVDD) POWER TRANSISTOR SUPPLY VOLTAGE (PVDD) POWER-DOWN CURRENT AVDD DVDD PVDD MUTE CURRENT AVDD DVDD PVDD OPERATING CURRENT AVDD DVDD PVDD Min 3.0 3.0 9 Typ 3.3 3.3 15 2 50 55 0.5 0.9 0.3 0.5 1.1 34 Max 3.6 3.6 18 3 55 600 0.6 1.2 0.9 0.6 2.5 40 Unit V V V A A A MUTE held low mA mA mA STDN and MUTE held high mA mA mA Test Conditions/Comments
STDN held low
Rev. 0 | Page 3 of 16
ADAU1513
DIGITAL I/O
Table 3.
Parameter INPUT VOLTAGE Input Voltage High Input Voltage Low OUTPUT VOLTAGE Output Voltage High Output Voltage Low LEAKAGE CURRENT ON DIGITAL INPUTS Min 2.0 0.8 2.4 0.4 10 Typ Max Unit V V V V A @ 2 mA @ 2 mA Test Conditions/Comments
PWM INPUT LOGIC TABLE
Table 4.
MUTE Low High High High High INL+/INR+ Low/High Low High Low High INL-/INR- Low/High Low Low High High OUTL+/OUTR+ Off GND PVDD GND PVDD OUTL-/OUTR- Off GND GND PVDD PVDD Mode High-Z Output damped Positive output Negative output Not used
DIGITAL TIMING
Table 5.
Parameter tSET tHOLD tWAIT tPDL-H tPDH-L tOUTx +/OUTx- MUTE Min 10 10 100 Typ Unit s s ns ns ns ns Description Wait Time for Unmute Wait Time for Shutdown Wait Time for Applying Input Propagation Delay (Low to High) Propagation Delay (High to Low) Time Delay After MUTE Held Low Until Output Stops Switching
13 13 600
STDN
tSET
MUTE INx+/INx- OUTx+/OUTx-
tWAIT tPDL-H
06750-002
tPDH-L
Figure 2. Timing Diagram Unmute
STDN
tHOLD
MUTE
INx+/INx-
06750-031
OUTx+/OUTx-
tOUTx+/OUTx- MUTE
Figure 3. Timing Diagram Mute
Rev. 0 | Page 4 of 16
ADAU1513 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter DVDD to DGND AVDD to AGND PVDD to PGND1 PWM Inputs MUTE/STDN Inputs Operating Temperature Range Storage Temperature Range Maximum Junction Temperature JA Thermal Resistance JB Thermal Characterization (Junction-Board) JT Thermal Characterization (Junction-Package Top) Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec)
1
Rating -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +20.0 V DGND - 0.3 V to DVDD + 0.3 V DGND - 0.3 V to DVDD + 0.3 V -40C to +85C -65C to +150C 150C 26.7C/W 13.3C/W 0.2C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
260C 215C 220C
Includes any induced voltage due to inductive load.
Rev. 0 | Page 5 of 16
ADAU1513 PIN CONFIGURATION AND FUNCTION DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37 PGND PGND PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PGND PGND
OUTL- 1 OUTL- 2 OUTL- 3 OUTL+ 4 OUTL+ 5 OUTL+ 6 INL- 7 INL+ 8 ERR 9 OTW 10 TEST2 11 TEST3 12
PIN 1 INDICATOR
ADAU1513
TOP VIEW (Not to Scale)
36 35 34 33 32 31 30 29 28 27 26 25
OUTR- OUTR- OUTR- OUTR+ OUTR+ OUTR+ TEST13 TEST12 TEST11 TEST10 TEST9 TEST8
NOTES 1. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND, DGND, AND AGND FOR TQFP-48. 2. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND AND DGND FOR LFCSP-48.
INR- INR+ MUTE STDN TEST4 TEST5 DGND DVDD AVDD AGND TEST6 TEST7
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number 1, 2, 3 4, 5, 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31, 32, 33 Mnemonic OUTL- OUTL+ INL- INL+ ERR OTW TEST2 TEST3 INR- INR+ MUTE STDN TEST4 TEST5 DGND DVDD AVDD AGND TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 OUTR+ Type 1 O O I I O O I I I I I I I O P P P P I I I I I I I I O Description Output of High Power Transistors, Left Channel Negative Polarity. Output of High Power Transistors, Left Channel Positive Polarity. Differential PWM Left Input (-). Differential PWM Left Input (+). Overtemperature Shutdown Error Indicator (Active Low Open-Drain Output). Overtemperature Warning Indicator (Active Low Open-Drain Output). Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DVDD. Differential PWM Right Input (-). Differential PWM Right Input (+). Mute (Active Low Input). Shutdown/Reset Input (Active Low Input). Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Do not connect. Digital Ground for Digital Circuitry. Internally connected to exposed pad (ePAD) 2 . Positive Supply for Digital Circuitry. Positive Supply for Analog Circuitry (Can be Tied to DVDD). Analog Ground for Analog Circuitry. Internally connected to ePAD2. Can be tied to DGND. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Output of High Power Transistors, Right Channel Positive Polarity.
Rev. 0 | Page 6 of 16
06750-003
ADAU1513
Pin Number 34, 35, 36 37, 38, 47, 48 39, 40, 41, 42, 43, 44, 45, 46
1
Mnemonic OUTR- PGND PVDD
Type 1 O P P
Description Output of High Power Transistors, Right Channel Negative Polarity. Power Ground for High Power Transistors. Internally connected to ePAD2. Positive Power Supply for High Power Transistors.
2
I = input, O = output, P = power. ePAD is connected internally to PGND, DGND, and AGND.
Rev. 0 | Page 7 of 16
ADAU1513 TYPICAL PERFORMANCE CHARACTERISTICS
-20
-20
-30
-30
-40
-40
-50
THD + N (dB)
100m 1 10
THD + N (dB)
-50
-60
-60
-70
-70
06750-004
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 5. THD + N vs. Output Power, 9 V, 4
-20
Figure 8. THD + N vs. Output Power, 12 V, 4
-20
-30
-30
-40
-40
THD + N (dB)
THD + N (dB)
-50
-50
-60
-60
-70
-70
06750-005
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 6. THD + N vs. Output Power, 9 V, 6
-20 -20
Figure 9. THD + N vs. Output Power, 12 V, 6
-30
-30
-40
-40
THD + N (dB)
THD + N (dB)
-50
-50
-60
-60
-70
-70
06750-006
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 7. THD + N vs. Output Power, 9 V, 8
Figure 10. THD + N vs. Output Power, 12 V, 8
Rev. 0 | Page 8 of 16
06750-009
-80 10m
-80 10m
100m
1
10
06750-008
-80 10m
-80 10m
100m
1
10
06750-007
-80 10m
-80 10m
100m
1
10
ADAU1513
-20 0 -10 -20 -30 -40 -50
OUTPUT (dBr)
0dBr = OUTPUT POWER AT 1% THD + N
-30
-40
THD + N (dB)
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150
-50
-60
-70
100m
1 OUTPUT POWER (W)
10
06750-010
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
Figure 11. THD + N vs. Output Power, 15 V, 4
-20 0 -10 -20 -30 -40
OUTPUT (dBr)
Figure 14. FFT, 1 W, 15 V, 8
0dBr = OUTPUT POWER AT 1% THD + N
-30
-40
THD + N (dB)
-50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150
-50
-60
-70
06750-011
0
2
4
6
8
10
12
14
16
18
20
OUTPUT POWER (W)
FREQUENCY (kHz)
Figure 12. THD + N vs. Output Power, 15 V, 6
-20 20 10 -30 0 -10 -20 -30
OUTPUT (dBV)
Figure 15. FFT, 60 dBFS, 15 V, 8
-40
THD + N (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130
-50
-60
-70
06750-012
0
2
4
6
8
10
12
14
16
18
20
OUTPUT POWER (W)
FREQUENCY (kHz)
Figure 13. THD + N vs. Output Power, 15 V, 8
Figure 16. FFT Dither, 15 V, 8
Rev. 0 | Page 9 of 16
06750-015
-80 10m
100m
1
10
-140
06750-014
-80 10m
100m
1
10
-160
06750-013
-80 10m
-160
ADAU1513
0 -5 -10 -15 -20
EFFICIENCY (%)
06750-016
90 80 70 60 50 40 30 20 10 20 100 1k FREQUENCY (Hz) 10k 0 5 10 15 20 25 30
06750-019 06750-021 06750-020
THD + N (dB)
-25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80
0
OUTPUT POWER (W)
Figure 17. THD + N vs. Frequency, 1 W, 15 V, 8
0 -10 -20 -30
CROSSTALK (dB)
Figure 20. Efficiency vs .Output Power, 15 V, 4
100 90 80 70
EFFICIENCY (%)
-40 -50 -60 -70 -80 -90 20 100 1k FREQUENCY (Hz) 10k
06750-017
60 50 40 30 20 10 0 0 5 10 15 20 25
LEFT TO RIGHT RIGHT TO LEFT
-100
OUTPUT POWER (W)
Figure 18. Crosstalk, 0 dBFS, 15 V, 8
6 100 90 5 80 70
EFFICIENCY (%)
Figure 21. Efficiency vs. Output Power, 15 V, 6
4
PDISS MAX (W)
60 50 40 30 20 10
3
2
1
06750-018
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 TAMBIENT (C)
0
0
5
10
15
20
25
OUTPUT POWER (W)
Figure 19. Power Dissipation vs. Ambient Temperature
Figure 22. Efficiency vs. Output Power, 15 V, 8
Rev. 0 | Page 10 of 16
ADAU1513
30 6 REQUIRES EXTRA HEAT-SINKING 4 5 6 20 8 15
POWER DISSIPATION (W)
25
OUTPUT POWER (W)
4
3
10
2
5
1
06750-022
6
7
8
9
10
11
12
13
14
15
16
17
18
0
5
10
15
20
25
PVDD (V)
OUTPUT POWER PER CHANNEL, STEREO MODE (W)
Figure 23. Output Power vs. PVDD, 40 dB THD + N
40 35 30
OUTPUT POWER (W)
Figure 26. Power Dissipation vs. Output Power, 6
3 4
POWER DISSIPATION (W)
25 20 15 10 5 0
6 8
2
1
6
7
8
9
10
11
12
13
14
15
16
17
18
0
5
10
15
20
PVDD (V)
OUTPUT POWER PER CHANNEL, STEREO MODE (W)
Figure 24. Output Power vs. PVDD, 20 dB THD + N
15 14 13 12
POWER DISSIPATION (W)
Figure 27. Power Dissipation vs. Output Power, 8
11 10 9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35
06750-024
0
OUTPUT POWER PER CHANNEL, STEREO MODE (W)
Figure 25. Power Dissipation vs. Output Power, 4
Rev. 0 | Page 11 of 16
06750-026
06750-023
0
06750-025
0
0
ADAU1513 THEORY OF OPERATION
OVERVIEW
The ADAU1513 is a 2-channel integrated power stage designed to accept the logic level PWM inputs. The PWM inputs are amplified, low-pass filtered using a simple passive LC network, and then can be used to drive the speaker loads. The power stage has built-in circuits for overtemperature, overcurrent, short-circuit, and undervoltage protection. This error flag is latched type. To restore the normal operation, MUTE (Pin 16) needs to be toggled to low and then to high again. The error flag is useful for the microcontroller in the system to indicate an abnormal operation and to initiate the audio MUTE sequence. The device senses the short-circuit condition on the outputs after the LC filter. Typical short-circuit conditions include shorting of the output load and shorting to either PVDD or GND.
POWER STAGE
The 2-channel ADAU1513 power stage comprises a total of eight half bridges. Each half bridge is made up of PMOS and NMOS devices. The gate drive for the respective FETs is generated internally and does not need a special gate drive supply or bootstrap capacitor compared to all NMOS stages. This simplifies the high-side driver design and requires less external components.
UNDERVOLTAGE PROTECTION
The ADAU1513 has an undervoltage protection circuit that senses the undervoltage on PVDD. When the PVDD supply goes below the operating threshold, the output FETs are turned to a high-Z condition. Also, the device issues an error flag by pulling the ERR pin low. This condition is latched. To restore the operation, MUTE (Pin 16) needs to be toggled to low and then to high again.
PROTECTION CIRCUITS
The ADAU1513 includes comprehensive protection circuits. It includes thermal warning, thermal overheat, and overcurrent or short-circuit protection on the outputs. The ERR and OTW outputs are open drain, requiring external pull-up resistors. The outputs are capable of sinking 10 mA. The open-drain outputs are useful in multichannel applications where more than one ADAU1513 are used. The error outputs of multiple ADAU1513s can be OR'ed to simplify the system design. The logic outputs of the error flags ease the system design using a microcontroller. The power stage does not consist of protection in case PWM input stays high continuously. In such a case, the output produces dc and it is possible to damage the speaker. To prevent this, ensure that the modulator is switching whenever the power stage is turned on.
AUTOMATIC RECOVERY FROM PROTECTIONS
In certain applications, it is desired for the amplifier to recover itself from thermal protection without the need for system microcontroller intervention. The ADAU1513 thermal protection circuit issues two error signals for this purpose: one thermal warning (OTW) and the other thermal shutdown (ERR). With these two error signals, there are two options for using the protections: * * Option 1: Using OTW Option 2: Using ERR
The following sections provide further details of these two options.
THERMAL PROTECTION
Thermal protection in the ADAU1513 is categorized into two error flags: one as thermal warning and the other as thermal shutdown. When the device junction temperature reaches near 135C (5C) the ADAU1513 outputs a thermal warning error flag by pulling OTW (Pin 10) low. This flag can be used by the microcontroller in the system as an indication to the user or can be used to lower the input level to the amplifier to prevent the thermal shutdown. The device continues operation until shutdown temperature is reached. When the device junction temperature exceeds 150C the device outputs an error flag by pulling the ERR (Pin 9) low. This error flag is latched. To restore the operation, MUTE (Pin 16) needs to be toggled to low and then to high again.
Option 1: Using OTW
The OTW pin is pulled low when the die temperature reaches 130C to 135C This pin can be wired to the MUTE pin using an RC circuit as shown in Figure 28.
ADAU1513
DVDD R1 100k OTW 10 C1 47F MUTE 15
D1 1N4148
TO MUTE LOGIC INPUT
Figure 28. Option 1 Schematic for Autorecovery
OVERCURRENT PROTECTION
The overcurrent protection in the ADAU1513 is set internally at 5 A peak output current. The device protects the output devices against excessive output current by pulling the ERR (Pin 9) low.
The low logic level on OTW also pulls down the MUTE pin. The bridge is shut down and, therefore, starts cooling or the die temperature starts reducing. When it reaches 120C, the OTW signal starts going high. While this pin is tied to a capacitor with a resistor pulled to DVDD, the voltage on this pin starts rising slowly towards DVDD. When it reaches the input logic high threshold, MUTE is deasserted and the
Rev. 0 | Page 12 of 16
06750-027
ADAU1513
amplifier starts functioning again. This cycle repeats itself depending on the input signal conditions and the temperature of the die. This option allows part operation that is safely below the shutdown temperature of 150C and allows the amplifier to recover itself without the need for microcontroller intervention.
POWER-UP/POWER-DOWN SEQUENCE
Figure 30 shows the recommended power-up sequence for the ADAU1513.
AVDD/DVDD
Option 2: Using ERR
Option 2 is similar to Option 1 if the ERR pin can be tied to MUTE instead of OTW. See the circuit in Figure 29.
ADAU1513
DVDD R1 100k ERR 9 C1 47F MUTE 15
PVDD STDN MUTE
tSET tWAIT
D1 1N4148
INx+/INx-
06750-029
TO MUTE LOGIC INPUT
OUTx+/OUTx-
06750-028
tPDL-H
Figure 30. Recommended Power-Up Sequence
Figure 29. Option 2 Schematic for Autorecovery
In this case, the part goes into shutdown mode due to any of the error-generating events like output overcurrent, overtemperature, missing PVDD or DVDD, or clock loss. The part recovers itself based on the same circuit operation in Figure 28. However, if the part goes into error mode due to overtemperature, then the device would have reached its maximum limit of 150C (15C to 20C higher than Option 1). If it goes into error mode due to an overcurrent from a short circuit on the speaker outputs, then the part will keep itself recycling on and off until the short circuit is removed. It is possible that, with this operation, the part is subjected to a much higher temperature and current stress continuously. This, in turn, reduces the part's reliability in the long term. Therefore, using Option 1 for autorecovery from the thermal protection and using the system microcontroller to indicate to the user of an error condition is recommended.
The ADAU1513 does not have any pop-and-click suppression circuits; therefore, care must be taken during the power-up. The power stage stays in Hi-Z on power-up. However, it is recommended to ensure that STDN and MUTE are held low during initial power-up. First, STDN should be pulled high followed by MUTE to turn on the power stage. The power stage turns on after the MUTE signal is pulled high and responds to PWM inputs after a small propagation delay of 200 s. The special turn-on sequence may be necessary depending on the PWM used to prevent the turn-on pop or click. However, if the ADAV4201 processor is used, the processor has a built-in special turn-on PWM sequence. The processor sends a unique PWM input start sequence that ensures soft turn-on. If another modulator is used, care must be taken to ensure that the modulator has built-in pop-and-click suppression. Also, because the power stage does not track the PWM inputs, it is recommended to use the system microcontroller to ensure that the modulator is ready to send the PWM sequence before turning on the power stage. Similarly, for muting the amplifier, it may be necessary to supply a special muting PWM sequence for minimum pop and click. The ADAV4201 processor has a built-in feature that takes care of this need. If any other modulator is used, care must be taken during muting of the power stage. The system microcontroller can be used to handle the mute/unmute of the power stage as well as a modulator. The error outputs of the power stage should be connected to the microcontroller port. This error flag can be used to inform the modulator that the power stage is shut down and to mute the PWM inputs. On removal of the error condition, the microcontroller should initiate an unmute sequence to minimize pop and click while power stage is turning on/turning off. The ADAU1513 uses three separate supplies: AVDD (3.3 V analog for internal reference), DVDD (3.3 V digital for control logic and clock oscillator), and PVDD (9 V to 18 V power stage and level shifter). Separate pins are provided for the AVDD,
MUTE AND STDN
The MUTE and STDN are 3.3 V logic-compatible inputs used to control the turn-on/turn-off for ADAU1513. The STDN input is active low when the STDN pin is pulled low and the device is in its energy-saving mode. The power stage is in high-Z state. The high logic level input on the STDN pin will wake up the device. The logic circuits are running internally but the power stage is still in high-Z state. When the MUTE pin is pulled high, the power stage is active and starts responding to PWM inputs. The low level on the MUTE pin disables the power stage and is recommended to be used to mute the audio output. See the Power-Up/Power-Down Sequence section for more details.
Rev. 0 | Page 13 of 16
ADAU1513
DVDD, and PVDD supply connections, as well AGND, DGND, and PGND. In addition, the ADAU1513 incorporates a built-in undervoltage lockout logic on DVDD as well as PVDD. This helps detect undervoltage operation and eliminates the need to have an external mechanism to sense the supplies. The ADAU1513 monitors the DVDD and PVDD supply voltages and prevents the power stage from turning on if either of the supplies are not present or below the operating threshold. Therefore, if DVDD is missing or below the operating threshold, for example, the power stage will not turn on, even if the PVDD is present or vice versa. Because this protection is only present on DVDD and PVDD and not on AVDD, shorting both AVDD and DVDD externally or generating AVDD and DVDD from one power source is recommended. This ensures both AVDD and DVDD supplies are tracking each other and avoids the need to monitor the sequence with respect to PVDD. This also ensures minimal pop and click during power-up. When using separate AVDD and DVDD supplies, ensure that both supplies are stable before unmuting or turning on the power stage. During power-up, it is recommended to keep STDN and MUTE low to ensure that the power stage stays in high-Z mode. Similarly, during shutdown, pulling MUTE to logic low before pulling STDN down is recommended. However, where a fault event occurs, the power stage will shut down to protect the part. In this case, depending on the signal level, there is some pop at the speaker. During shutdown of the power supplies to reduce power consumption, it is highly recommended to mute the amplifier first, followed by pulling STDN low before shutting down any of the supplies. After MUTE is pulled low, the power supplies can be shut down in the following order: PVDD, DVDD, then AVDD. Where AVDD and DVDD are generated from a single source, ensure that PVDD is tuned off before DVDD and AVDD, and after issuing MUTE and STDN.
Rev. 0 | Page 14 of 16
ADAU1513 APPLICATIONS INFORMATION
Refer to the application schematic in Figure 31 for details on connections and component values. For details on the PWM modulator part, refer to the ADAV4201 data sheet. For applications with PVDD > 15 V, add components R1 and R2 = 10 typical, C5 and C6 = 680 pF typical, and D1 through D8 = CRS01/02.
3.3V
PVDD
100nF
100nF
100nF
100nF
470F
1F
TEST3
AVDD
DVDD
PVDD
PVDD D1 D2 INL+ PULSE-WIDTH MODULATOR INL- INR+ INR- OUTL- PVDD D3 D4 PVDD D5 D6 PVDD OUTR- D7 D8 R2 10 C6 680pF L3 C3 R1 10 C5 680pF L1 C1
OUTL+
ADAV4201
SDA SCL
L2 C2
OUTR+
ADAU1513
I2C CONTROL
L4 C4
SYSTEM LOGIC CONTROL OR MICROCONTROLLER
STDN MUTE ERR OTW
TEST10 TEST11 TEST12 TEST13 TEST2 TEST4 TEST6 TEST7 TEST8 TEST9 AGND DGND PGND
Figure 31. Application Schematic
Table 8. Suggested Low-Pass Filter Values
Load Impedance () 4 6 8 Inductance L1 to L4 (H) 10 15 22 Capacitance C1 to C4 (F) 1.5 1 0.68
Rev. 0 | Page 15 of 16
06750-030
ADAU1513 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 32. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters
0.75 0.60 0.45 1.00 REF SEATING PLANE
1.20 MAX
48 1 PIN 1
9.20 9.00 SQ 8.80
37 36 37 36
BOTTOM VIEW
(PINS UP) 48 1
TOP VIEW
(PINS DOWN) EXPOSED PAD 12 13 25 24 25 24 12 13
5.10 SQ
1.05 1.00 0.95
7.20 7.00 SQ 6.80
0.20 0.09 7 3.5 0
VIEW A
0.15 0.05
0.50 BSC LEAD PITCH
0.08 MAX COPLANARITY
0.27 0.22 0.17
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ABC
Figure 33. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-48-5) Dimensions shown in millimeters
ORDERING GUIDE
Model ADAU1513ACPZ 1 ADAU1513ACPZ-RL1 ADAU1513ACPZ-RL71 ADAU1513ASVZ1 ADAU1513ASVZ-RL1 ADAU1513ASVZ-RL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
042507-A
VIEW A
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13" Tape and Reel 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 13" Tape and Reel 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 7" Tape and Reel
Package Option CP-48-1 CP-48-1 CP-48-1 SV-48-5 SV-48-5 SV-48-5
Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06750-0-5/07(0)
Rev. 0 | Page 16 of 16

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